1. Field of the invention
The present invention relates to a one-transistor type memory cell for use in DRAMs (dynamic random access memory), and more specifically to such a one-transistor type memory cell having an associated information storage capacitor.
2. Description of related art
In the prior art, a one-transistor type memory cell having an associated information storage capacitor such as a stacked capacitor has been known, which includes a MOSFET (metal-oxide-semiconductor field effect transistor) formed in a device formation zone confined by a field oxide on a principle surface of a semiconductor substrate. The MOSFET includes a pair of diffusion regions which are formed in the principle surface of the semiconductor substrate, separately from each other so as to form a channel between the pair of diffusion regions. The pair of diffusion regions constitute a source region and a drain region of the MOSFET. An oxide layer is formed to cover the principle surface of the semiconductor substrate within the device formation zone, and a word line is formed on the oxide layer so as to pass above the channel formed between the source region and the drain region. Therefore, a portion of the word line passing above the channel formed between the source region and the drain region functions as a gate electrode, and a portion of the oxide layer between the gate electrode and the channel functions as a gate oxide.
The gate electrode and the oxide layer which is not covered with the gate electrode, are covered with a lower interlayer insulator layer. An opening is formed in the lower interlayer insulator layer at a position of the drain region, and a storage electrode is formed to extend over the lower interlayer insulator layer and to contact with the drain region in the opening formed in the lower interlayer insulator layer. A capacitor electrode is formed over the storage electrode with a capacitor insulator film being sandwiched between the storage electrode and the capacitor electrode. Thus, a stacked capacitor is formed of the storage electrode, the capacitor insulator and the capacitor electrode.
In addition, an upper interlayer insulator layer is formed to cover the stacked capacitor, and a bit line is formed on the upper interlayer insulator layer. This bit line is connected to the source region through a contact hole formed in the upper and lower interlayer insulator layer above the source region.
Thus, the one-transistor type memory cell connected to the word line and the bit line is formed. In this one-transistor type memory cell, the storage electrode is ordinarily formed of a polysilicon. In order to cause the storage electrode to have sufficient conductivity, the polysilicon of the storage electrode has been diffused with impurities. In this diffusion process, the impurities diffuse not only into the storage electrode but also into the semiconductor substrate. As a result, another diffusion region has been inevitably formed within the drain region in the semiconductor substrate. This second diffusion region has a depth larger than that of the drain region. In other words, the second diffusion region extends into the semiconductor substrate beyond a bottom of the drain region.
Formation of the above mentioned second diffusion region has given significant adverse affects. First, the impurities diffused into the semiconductor substrate will lower a threshold voltage of a parasitic transistor formed in proximity of the field oxide, so that a device isolation function is deteriorated. In addition, a threshold of a transistor connected to the word line is also decreased. This influence becomes further remarkable if a memory capacity is increased and a cell size is reduced. Therefore, the formation of the second diffusion region is inconvenient to microminiaturization of semiconductor memories.
In view of the above problems, concentration of the impurities diffused to the storage electrode of the stacked capacitor has been restrained to a low level in the prior art.